The International Symposium on Computer Architecture (ISCA) Workshop on "ARM General-Purpose Computing: Software-Hardware Co-Optimization for Performance Acceleration" aims to bring together researchers, engineers, and industry leaders to explore the latest advancements and innovations in leveraging ARM architecture for high-performance general-purpose computing in data center. With the growing importance of ARM-based systems in data centers and beyond, this workshop focuses on the synergy between software and hardware to achieve significant performance gains. We invite contributions that address novel algorithms, new benchmarks regarding performance and power, microarchitectural designs, hardware accelerators, tightly-coupled architectures, and optimization techniques tailored for ARM instruction set architecture. This workshop seeks to foster a collaborative environment where participants can share insights, challenges, and solutions to drive the future of ARM-based general-purpose computing.
Workshop Agenda:
Time
Topic
Speakers
Institution
14:00 - 14:20
Accelerating Hash Aggregate for Big Data Analytics
Anirban Nag
Huawei Zurich Research Center
14:20 - 14:40
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms
Julian Pavon Rivera
BSC
14:40 – 15:00
QFlex 3.0: Fast and Accurate ARM Server Simulation
Ali Ansari
EPFL
15:00 - 15:20
On the Use of Fujitsu A64FX Processor for Genome Sequence Analysis Workloads
Julian Pavon Rivera
BSC
15:20 – 15:40
Memory Access Vectors: Improving Sampling Fidelity for CPU Performance Simulations
Workload-driven Architecture Design and System Performance Optimization (Invited talk)
Prof. Zhibin Yu
Shenzhen Institute of Advanced Technology
Important Dates
Paper Submission Deadline: April 30, 2025 May 15, 2025
Notification of Acceptance: May 15, 2025 May 21, 202
Camera-Ready Submission: May 30, 2025
Workshop Date: June 21, 2025
Topics of Interest
Innovative Data Engineering Algorithms Based on ARM Instruction Set and Pipeline:
Exploration of efficient algorithms optimized for ARM instruction sets and pipeline characteristics.
Techniques for leveraging ARM-specific features to enhance data processing and improve throughput.
Workload characterization for ARM-based enterprise applications including big data and AI applications.
Case studies on real-world applications and performance improvements.
Single-Core and Multi-Core High-Performance Microarchitecture Design for Typical Data Center Scenarios:
Design principles for Single-Core and Multi-Core performance of ARM-based data center processors targeting high performance in data center environments.
Techniques to optimize instruction-level parallelism, branch prediction, and cache utilization.
Evaluation of microarchitectural innovations through simulation and benchmarking.
Multi-core/SoC architecture design for highly multi-threaded data center applications:
Synchronization characterization of highly multi-threaded data center applications.
Network-on-chip design for multi-core architectures.
NUMA effect optimizations.
Hardware Accelerator Design for Data Center Typical Scenarios:
Development of specialized hardware accelerators tailored for ARM-based systems in data centers.
Integration of accelerators with ARM processors to offload compute-intensive tasks.
Case studies on accelerator deployment and performance benefits in typical data center workloads.
Architecture and Application Tightly-Coupled Innovation for Typical Data Center Scenarios:
Exploration of tightly-coupled architectures that integrate ARM processors with other components (e.g., memory, accelerators).
Techniques for optimizing data flow and reducing latency in tightly-coupled systems.
Real-world applications and performance evaluations of tightly-coupled architectures in data centers.
ARM Instruction Stream Trace Analysis and Optimization:
Methods for tracing and analyzing ARM instruction streams to identify performance bottlenecks.
Techniques for optimizing instruction sequences and improving execution efficiency.
Tools and frameworks for instruction stream analysis and optimization in ARM-based systems.
Submission Guidelines
AGPC welcomes submissions of short papers, up to 3 pages excluding references, using a double-column format. You can use this Latex template.
Submissions should state the research problem, motivation, and technical contribution. All submissions must be in English. The submissions should be sent in a single PDF file.
Papers can present work in progress, exploratory/preliminary research, or already published work.
Submissions will be assessed based on their novelty, technical quality, potential impact, interest, clarity, relevance, and reproducibility.
Reviews will not be blind, so please submit without anonymizing authors in the submitted PDF.
There will be no formal proceedings; papers will be posted on the workshop website, allowing authors the flexibility to extend and publish their work in other conferences and journals.
For each accepted paper, at least one author must attend the workshop and present the paper.
