As semiconductor technologies continue to advance and chiplet integration becomes more widespread, the demand for highly reliable systems has never been greater. Modern chips face increasing susceptibility to various reliability-related mechanisms (described by different fault models) such as manufacturing defects, device variability, marginalities, aging, voltage drop. These faults pose significant challenges to the design of robust systems, as their impact can cascade from the physical level to the overall system level, affecting architecture, software, performance, functionality, and safety and leading to systems that either observably don’t operate (crash) or, even worse, produce unnoticed corrupted outputs (silent errors, silent data corruptions). To address these challenges, there is a pressing need for efficient modeling and simulation frameworks that can accurately capture and analyze the effects of these fault mechanisms across multiple abstraction levels.
This workshop aims to bring together researchers, practitioners, and industry experts to discuss state-of-the-art techniques for modeling, simulation, and on top of them mitigation of reliability-related mechanisms in modern silicon chips and systems built on them. We invite contributions that explore innovative approaches to fault modeling, simulation environments, and methodologies for evaluating and improving system reliability in the presence of silicon faults and marginalities.
Important Dates
Paper Submission Deadline: April 30, 2025
Notification of Acceptance: May 15, 2025
Camera-Ready Submission: May 30, 2025
Workshop Date: June 21, 2025
Topics of Interest
Fault modeling for physical fault mechanisms and their impact on system architecture, performance, safety, and resilience.
Fault effects (such as Silent Data Corruptions – SDC) modeling and mitigation techniques with emphasis on hyperscale systems.
Cross-layer simulation frameworks for reliability analysis (from physical to system level).
Reliability-aware modeling and simulations for chiplet-based systems.
Machine learning and AI-based approaches for fault prediction and reliability modeling.
Tools and techniques for simulation of fault injection and failure scenarios in general-purpose processors and domain-specific accelerators.
Case studies of fault injection simulation and reliability challenges.
Reliability evaluation, modeling, and simulation for safety-critical systems and applications.
Submission Guidelines
ReMoS welcomes submissions of short papers, up to 3 pages excluding references, using a double-column format. You can use this Latex template.
Submissions should state the research problem, motivation, and technical contribution. All submissions must be in English. The submissions should be sent in a single PDF file.
Papers can present work in progress, exploratory/preliminary research, or already published work.
Submissions will be assessed based on their novelty, technical quality, potential impact, interest, clarity, relevance, and reproducibility.
Reviews will not be blind, so please submit without anonymizing authors in the submitted PDF.
There will be no formal proceedings; papers will be posted on the workshop website, allowing authors the flexibility to extend and publish their work in other conferences and journals.
For each accepted paper, at least one author must attend the workshop and present the paper.
